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5.5 CMOS Logic Gates - Introduction to Digital Systems: Modeling, Synthesis, and Simulation Using VHDL [Book]
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Ultrafast CMOS inverter with 4.7 ps gate delay fabricated on 90 nm SOI technology | Semantic Scholar
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mosfet - Analyzing circuit that cascades a pseudo NMOS inverter with a CMOS inverter - Electrical Engineering Stack Exchange
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